1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to semiconductor wiring structures including a local dielectric cap within a metal cap layer.
2. Background Art
In the integrated circuit (IC) chip fabrication industry, electromigration (EM) induced failure in interconnects is a major concern for advanced back-end-of-line (BEOL) technology. Early EM induced failure, in particular, significantly reduces the projected current limit of product chip under operating conditions. EM induced failure, particularly in interconnects fabricated using a dual-damascene process, may take the form of “line-fails” or “via fails.” The arrow in FIG. 1A shows the electron current flow and the EM flux. It is well known that, in a dual-damascene interconnect, an electron current flowing from via 10 into a line 32 above can induce EM damage in either via 10 and/or line 32, causing via voiding 14 or line voiding 30, respectively, as shown in FIG. 1B. Via voiding 14 results in very early fail under EM conditions during circuit operation, since it takes only a very small void 14 at the bottom of via 10 to cause an open circuit and failure in such a case. Line voiding 30, on the other hand, results in late fails, since the associated void size required to cause an electrical open is significantly larger.